Research

Reconfigurable computing, FPGA accelerators, and the CAD tools that make dynamically reconfigurable SoCs practical to build.

My work spans the stack of reconfigurable system design: the optimization algorithms that decide how a design is laid out on the fabric, the design flows and open-source platforms that turn a specification into a working SoC, and the applications — neural network inference, edge computing, fault tolerance, security — that motivate the whole exercise.

Dynamic partial reconfiguration (DPR) lets an FPGA swap accelerators in and out of a running system, but the vendor flows for it are manual, brittle, and hard to combine with a full SoC stack. PR-ESP extends the open-source ESP platform so that a designer can specify reconfigurable regions at the system level and get a complete, working SoC — bitstream generation, reconfiguration management, and the software API to drive it — without hand-editing the vendor flow.

• System-level specification of reconfigurable regions and the accelerators that share them
• Automated generation of partial bitstreams and the runtime that loads them
• A device-driver and software API so applications can request accelerators by name

Placing reconfigurable regions on an FPGA is a constrained geometric optimization problem: regions must be rectangular, clock-region aligned, resource-sufficient for every accelerator that will occupy them, and non-overlapping. FLORA formulates this as an optimization problem and solves it automatically, replacing the trial-and-error floorplanning that otherwise dominates DPR design time. A companion flow extends this to full hardware–software co-design under DPR.

• Automatic floorplanning of reconfigurable areas under resource and shape constraints
• Design-flow automation for HW/SW co-design on FPGA SoCs under DPR
• Published in ACM TECS and ACM SAC

A deep network rarely fits on a mid-range FPGA all at once. If the fabric can be reconfigured while the system runs, the network's layers can be mapped onto a small set of regions that are reloaded over time — trading reconfiguration latency for area. Getting this right means optimizing the spatial partitioning and the temporal schedule together, which is what this work formulates and solves.

• Joint spatial–temporal optimization of DNN mapping onto reconfigurable regions
• Accounts for reconfiguration overhead as a first-class cost
• Published in IEEE Transactions on Computers

Modern SoCs integrate IP blocks from many vendors onto a shared network-on-chip, which makes a single malicious or buggy block a system-wide problem. BASTION defines a framework for integrating third-party IP into NoC-based SoCs with enforceable isolation. In a related direction, OPEN-CFR uses dynamic partial reconfiguration as the mechanism for redundancy and repair in commercial off-the-shelf FPGA SoCs — the kind of part that flies in space systems where radiation-induced faults are expected rather than exceptional.

• Secure integration of untrusted third-party IP in NoC-based SoC platforms
• DPR-based redundancy and recovery for COTS FPGA SoCs
• Collaboration with UC San Diego (Kastner Research Group)

Edge systems have to meet real-time deadlines on a power budget, which is exactly the case for hardware acceleration — provided the software can actually reach the accelerators predictably. EigenEdge addresses that execution model on RISC-V SoCs. MindCrypt takes a different angle on brain-computer interfaces: neural signals are noisy and non-reproducible, which makes them a candidate entropy source for the cryptography running on the same SoC.

• Real-time software execution on RISC-V SoCs with hardware accelerators
• Neural signals as an entropy source for SoC-based brain-computer interfaces
• Published at CPS-IoT Week and IEEE ICCD

Earlier work, from my time in Trento: a bolt that monitors its own preload and reports wirelessly, powered entirely by harvested energy. The design problem is a hard energy budget — the sensing, computation, and radio all have to fit inside what the harvester produces, so the system is energy-neutral over its duty cycle rather than merely low-power.

• Energy-neutral operation from harvested energy, no battery replacement
• Instrumented fastener for safety-critical structural monitoring
• Published in MDPI Sensors and at the Global IoT Summit