Biruk B. Seyoum — Associate Research Scientist

About

Biography

I am an Associate Research Scientist in the System-Level Design Group at Columbia University, where I work with Prof. Luca P. Carloni and serve as lead architect of ESP, the group's open-source platform for heterogeneous system-on-chip design. My research sits at the intersection of reconfigurable computing and system-level design: I build the CAD algorithms, design flows, and open-source platforms that make dynamically reconfigurable FPGA SoCs practical to design, program, and trust.

I received my Ph.D. from the Real-Time Systems (ReTiS) Laboratory at Scuola Superiore Sant'Anna in Pisa, Italy, where my dissertation developed design methods for partially reconfigurable FPGA-based SoCs and applied them to accelerating deep neural networks. Before that I earned an M.Sc. in Telecommunications and Electronics from the University of Trento and a B.Sc. in Electrical and Computer Engineering from the Addis Ababa Institute of Technology.

Much of my work ships as open source. Alongside ESP itself, that includes PR-ESP, which brings dynamic partial reconfiguration to the platform, and FLORA, a floorplanner for reconfigurable regions on FPGA fabric.

Research interests

Reconfigurable computing
FPGA accelerators
FPGA CAD tools
System-level design
Heterogeneous SoC architectures
FPGA-based DNN acceleration

Open source

Projects

ESP

Embedded Scalable Platforms Lead architect

Heterogeneous SoC architecture and IP integration made easy.

ESP is an open-source research platform for heterogeneous system-on-chip design that pairs a scalable tile-based architecture with a system-level design methodology. A multi-plane network-on-chip connects processor, accelerator, memory, and I/O tiles, while a set of platform services — DMA, distributed interrupts, and runtime selection of the cache-coherence model — lets an accelerator drop into a working SoC without anyone redesigning the interconnect around it. The payoff is a full-system FPGA prototype in hours instead of months, which is why it is used for research and teaching well beyond Columbia.

Tile-based architecture over a multi-plane NoC: processor, accelerator, memory, and I/O tiles compose without touching the interconnect
Three processor choices — Ariane (64-bit RISC-V), Ibex (32-bit RISC-V), and LEON3 (SPARC V8)
Accelerators from SystemC, C/C++, Chisel, hls4ml, or plain RTL, plus third-party IP such as NVIDIA's NVDLA
Platform services for DMA, distributed interrupts, and runtime coherence selection
Targets Xilinx VCU118, VCU128, ZCU102, ZCU106 and VC707 boards, proFPGA modules, and an ASIC flow

RISC-V
Network-on-chip
FPGA
ASIC
SystemC
Chisel
HLS
Accelerators

422GitHub stars

144Forks

2019Open source since

Apache 2.0License

Repository figures as of August 2026.

esp.cs.columbia.edu GitHub repository Documentation Tutorials ESP publications ESP talks Teaching with ESP Team

PR-ESP

Lead author

Partially Reconfigurable ESP

An extension of ESP that lets a designer declare reconfigurable regions at the system level and receive a complete working SoC — partial bitstreams, the runtime that loads them, and the software API to request accelerators by name — without hand-editing the vendor flow.

DPR
FPGA
SoC

DATE 2023 paper CASES 2022 paper

FLORA

Lead author

Floorplan Optimizer for Reconfigurable Areas

Placing reconfigurable regions is a constrained geometric problem — rectangular, clock-region aligned, resource-sufficient, non-overlapping. FLORA solves it as an optimization problem instead of by trial and error, removing what is otherwise the slowest step in a DPR design.

CAD
Optimization
FPGA

ACM TECS paper

Impact

Citation metrics

108 Citations 102 since 2021

6 h-index 5 since 2021

3 i10-index 3 since 2021

Source: Google Scholar, as of August 2026.

Research

What I work on

Partially Reconfigurable Heterogeneous SoCs

Open-source platforms and design flows that bring dynamic partial reconfiguration to heterogeneous SoCs.

CAD and Floorplanning for Reconfigurable Fabric

Optimization algorithms that decide where reconfigurable regions physically go on the die.

Accelerating Deep Neural Networks on Reconfigurable Fabric

Scheduling DNN layers across time-multiplexed reconfigurable regions to fit big networks on small FPGAs.

Selected publications

BASTION: A Framework for Secure Third-Party IP Integration in NoC-based SoC Platforms

Francesco Restuccia, Zhenghua Ma, Joseph Zuckerman, Andres Meza, Biruk Seyoum, Luca Carloni, Ryan Kastner

IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), vol. 2025, no. 4, pp. 317–340, 2025.

Journal DOI 2 citations

PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs

Biruk Seyoum, Davide Giri, Kuan-Lin Chiu, Bryce Natter, Luca Carloni

Design, Automation & Test in Europe Conference (DATE), pp. 1–6, 2023.

Conference DOI PDF 9 citations

Automating the Design Flow under Dynamic Partial Reconfiguration for Hardware-Software Co-Design in FPGA SoC

Biruk Seyoum, Marco Pagani, Alessandro Biondi, Giorgio Buttazzo

ACM Symposium on Applied Computing (SAC), pp. 481–490, 2021.

Conference DOI 17 citations

Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs

Biruk Seyoum, Marco Pagani, Alessandro Biondi, Sara Balleri, Giorgio Buttazzo

IEEE Transactions on Computers, vol. 70, no. 11, pp. 1988–2000, 2021.

Journal DOI 38 citations

FLORA: Floorplan Optimizer for Reconfigurable Areas in FPGAs

Biruk B. Seyoum, Alessandro Biondi, Giorgio C. Buttazzo

ACM Transactions on Embedded Computing Systems (TECS), vol. 18, no. 5s, pp. 1–20, 2019.

Journal DOI 22 citations

All 14 publications

Updates

Recent news

Oct 2025
“Lightweight Congruence Profiling for Early Design Exploration of Heterogeneous FPGAs” presented at IFIP/IEEE VLSI-SoC 2025.
Sep 2025
BASTION published in IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES 2025, issue 4).
Jun 2025
Our SoC-engineering course experience report appeared at the Workshop on Computer Architecture Education (WCAE 2025).
Jul 2024
Open-CFR presented at the IEEE Space Computing Conference — DPR-based redundancy for COTS FPGA SoCs.
Apr 2023
PR-ESP presented at DATE 2023: an open-source platform for designing and programming partially reconfigurable SoCs.

Get in touch

Contact

Email

bs3302 [at] columbia.edu

Office

Department of Computer Science, Columbia University
New York, NY

Elsewhere

ESP project · GitHub · Google Scholar · ACM Digital Library · LinkedIn · SLD Group · Personal blog